Strategic advisor to early-stage VLSI chip startups using AI to redesign hardware processes for memory, power, and compute efficiency. Nearly two decades of full chip lifecycle experience at Qualcomm (San Diego) and Intel (Bangalore) — spanning IP conception, architecture, design, verification, and SoC integration across modem, server, and client families. Brings a rare dual perspective as both IP provider and IP consumer, and hands-on experience piloting AI-assisted verification workflows. Advisory focus: verification strategy, AI integration discipline, memory/power coverage, program execution, and team design Not hands-on execution — clear-eyed strategic guidance.
21%Fewer bug escapes
17%Fewer milestone delays
15%Operational cost saved
40+IPs migrated to industry tools
9+Concurrent SoCs managed
4×Faster engineer ramp-up
Advisory practice
NUM by Mala Masti — malamasti.com
2025 – Present
Founder & Hardware Advisor
- Strategic advisory for early-stage VLSI chip startups on verification strategy, AI tool integration, memory/power efficiency coverage, and IP program execution
- Help founders and engineering leads define quality gates, coverage architecture, post-silicon traceability, and AI adoption governance before these become tapeout blockers
- Advise on EDA toolchain decisions, vendor evaluation, team structure, and onboarding for growing design verification teams
Industry experience
Intel, Bangalore
Jan 2018 – Jul 2025
Program Manager & Design Verification Engineering Manager · Xeon server (Sapphire/Emerald/Granite/Diamond Rapids) | Core Ultra client (Meteor/Panther/Tiger/Nova Lake)
- Ran IP programs for 9+ concurrent SoCs across server, client, graphics, and network business units; acted as Chief-of-Staff to engineering leadership translating roadmaps into OKRs
- Owned verification for DFT IP families (IEEE 1687/IJTAG, IEEE 1149.1/JTAG) across 3+ chip generations; verified AMBA/AXI bridging components and MIPI 2.0-compliant IPU data-paths
- Migrated 40+ IPs from proprietary to industry-standard toolchains (VCS, QuestaSim, Xcelium, Tessent ICL-PDL) without disrupting delivery schedules
- Established post-silicon bug traceability back to IP quality gaps; closed feedback loop with upstream verification to prevent recurrence across all co-affected SoCs
- Explored AI-assisted log parsing to extract simulation error codes, identifying where automated triage can accelerate debugging — and where engineering judgment remains essential./li>
- Designed sensor-agnostic Telemetry flows for silicon-defect detection; built shared training infrastructure compressing onboarding from 6 months to 6 weeks
- Engaged external service providers for staff augmentation; negotiated and maintained SOWs; mentored engineers on career growth and systems thinking
Qualcomm Inc, San Diego, USA
Sep 1994 – Feb 2006
Staff Engineer — Architecture, Design, Verification · MSM 2200–7500 series: 15+ SoCs across 2G/2.5G/3G/early 4G
- Full lifecycle ownership of modem IPs (channel de-interleaver, searcher, finger front-end demodulator) across IS-95, IS-2000, and WCDMA/UMTS standards from architecture to post-silicon
- Built 98% of the QCT VHDL standard cell library used in simulation and synthesis across 2G/3G chip families
- Demonstrated live 3G/4G modem IPs to high-stakes customers in real-time lab environments; contributed to global product-launch feature planning for multi-tiered markets
- Researched power-area-performance trade-offs for product roadmap planning beyond 3G
Academia & EdTech Startups, Bangalore
Jun 2006 – Jan 2018
Visiting Faculty (Jain University) · Consultant · STEAM Tutor-Coach
- Taught 'Intro to Digital Design' (MTech VLSI) and Probability-Statistics (MCA/MSc) at university level; guided capstone projects and master theses
- Trained and mentored university students into interns or full-time positions across chip product, services and EDA companies
- Conducted operational feasibility studies and curated structured learning programs for EdTech and Logistics startups
Core competencies
Advisory focusVerification strategy · AI integration governance · Memory/power coverage · IP lifecycle · Program execution · Team architecture
ProtocolsIEEE 1687/IJTAG · IEEE 1149.1/JTAG · AMBA/AXI · MIPI 2.0 · Telemetry sensor interfaces · 2G/3G/4G cellular (IS-95, IS-2000, WCDMA)
VerificationVCS/Verdi · QuestaSim · Xcelium · UVM/SystemVerilog · Tessent ICL-PDL · Coverage planning · Testbench architecture
Program mgmtOKRs/KPIs · Milestone tracking · Risk escalation · Vendor/SOW governance · Executive reporting · Multi-site coordination
ToolsJira · Power-BI · Perl · Tcl · Shell · Python (basic) · SQL · AI-prompting (Anthropic, OpenAI, Google, IBM)
Education
M.S. Electrical Engineering
Virginia Tech, USA
B.Tech Electrical Engineering
IIT Bombay, India
Awards & recognition
President of India Gold Medal — Top 25, National Physics Olympiad
NTSE National Scholarship — High School through Undergraduate
Intel Division Recognition (multiple) · Qualcomm Qual-Star Awards
AI upskilling in progress: Anthropic, OpenAI, Google, IBM, MIT, Coursera