Chip advisory · Bengaluru & global

From inside chip products
to helping start-ups

Advisor for early-stage chip and EDA start-ups — team structure, verification strategy and program execution, drawn from shipping several SoCs and IPs at Qualcomm and Intel

See advisory areas About Mala

20+

Years across full chip life cycle — IP conception to post-silicon, spanning Qualcomm, Intel, and academia

40+

IPs owned, verified, and taped-out across Xeon data server, Core Ultra Client, Graphics, Gaming, Image Processing, DFT, Telemetry, Network Edge and MSM Modem families

80+

IP variant programs managed across multi-site global teams overall, delivering across 10+ concurrent SoCs in parallel

What is NUM

Beyond mentoring - networks, resources and more

NUM - Network · Unblock · Mentor - a trusted partner for founders

🧭

Network

Bringing two decades of the ecosystem - engineering talent, EDA vendors, domain experts - to grow your footprint in the silicon world

🔓

Unblock

Offering a fresh angle to problems - technical limitations, execution challenges, tool issues, interface incompatibilities, real-world constraints

🎯

Mentor

Helping engineers - think, plan, set up frameworks, prioritize features, define measurable outcomes, identify milestones and the like

Who this is for

Early-stage teams optimizing
tools or building silicon

NUM advisory is a fit if any of these describes your situation.

First-time hardware founding team

Your team is technically sound and can benefit with some practical perspectives and tested examples from experiential lessons

Scaling a small DV team

You're growing your design verification team and want to scale your onboarding structure, shared infrastructure, keeping quality intact

Inherited IP, unknown risk

You're integrating third-party or legacy IPs into your SoC and need insights on what to look for, what can go wrong

Exploring AI in your verification flow

You're piloting AI flows and need help designing various scenarios and bench-marking several possibilities for optimal performance

Custom expertise requirements

You need experienced talent with specific in-depth protocol know-how or you need engineers with varied, broad functional exposure

Staying on course

You want to offload monitoring progress, tracking inter-dependencies, managing task lists, closing communication gaps, mitigating risks

Advisory areas

Learnings I can share

A few example focus areas to help teams chart a smoother path ahead, clear of common pain points

Verification strategy

Quality checks for phased releases

Defining metrics for intermediate project stages with backward-compatibility checks, sign-off criteria, selective deploying of formal verification, gradual build-up of test cases helps pace team activities with a positive momentum.

AI adoption in verification

Time-tested old school - always reliable

Enabling AI-assisted log parsing for simulation debugging confirmed that manual cross-verification remains a best practice worth keeping, even as AI capabilities keep evolving.

IP quality

Post-silicon traceability

Back-tracing post-silicon bug requires root-causing it to specific IP version(s), enhancing tests to detect its recurrence, and then ensuring the corrected, fixed IP version is rolled into all co-affected SoCs in subsequent SoC-revisions.

Program execution

Milestone & risk discipline

Constant active participation in relevant forums is needed to become aware early of potential risks, schedule slips and later escalation of urgent issues to quickly resolve them is a must to minimize the impact to pre-committed milestone timelines.

Toolchain decisions

EDA tool strategy & migration

Adopting a mix of low-maintenance industry-standard tools as well as yet-to-be-re-purposed, high-maintenance, proprietary, custom scripts is needed at times for a low-risk, timely completion of complex automation processes in existing IP release flows

Team & org

Building & onboarding DV teams

Designing cross-site onboarding programs and building a strong, results-driven team-culture goes a long way in connecting teams with unified, shared ownership.

About Mala

A journey through
generations of chips

Mala S Masti

I have worked for nearly 12 years at Qualcomm, San Diego on the MSM modem series — from conception through post-silicon, across 2G, 2.5G, 3G, and early 4G. I have owned several IPs end-to-end - architecting, designing, coding, verifying, documenting and demonstrating live a few IPs to high-stakes customers in real-time lab environments.

I have spent a little over 7.5 years at Intel, Bangalore, running IP programs for over 10 concurrent SoCs at a time across Xeon data server, Core Ultra Client, Graphics, Gaming, DFT, Telemetry and Network Edge SoCs. I have held roles of Design Verification Engineering Manager, Design Automation Engineer and IP Program Manager which helped me gain a close-up view of the gaps between customer expectation and product quality as well as between a technically-driven option and a business-oriented choice. I have thus learned along the way to handle conflicting pressures for defining scope, planning schedule and aligning stakeholders

Additionally I have mentored many university undergraduate and graduate engineering students to get hired as interns and/ or full-time engineers at various hardware product/ service companies in Bangalore.

I now help a few start-ups, sharing what I have learned so far - enabling them to make better, informed decisions.

Qualcomm — Staff Engineer Intel — DV EM & Program Manager

IIT Bombay — B.Tech Virginia Tech — M.S.

President of India Gold Medal NTSE National Scholarship

LinkedIn ↗ GitHub ↗ Resume ↗

From inside chip productsto helping start-ups